The present invention relates to a method for manufacturing an electronic device having an element including a ferroelectric film or a high dielectric constant film (hereinafter, referred to as high-k film).
Recently, non-volatile or high-capacity semiconductor memory elements having a thin film formed from an insulating metal oxide (such as a ferroelectric material or a high dielectric constant material (a dielectric material having a high dielectric constant; hereinafter, referred to as high-k material)), especially, a substance having a perovskite crystal structure, are increasingly developed. The use of hysteresis characteristics of a ferroelectric film enables implementation of a non-volatile memory. Moreover, the use of a high-k film having a much greater dielectric constant than a silicon oxide film as a capacitor insulating film enables reduction in memory cell area, and thus enables implementation of a highly-integrated high-capacity RAM (Random Access Memory). Typical materials which are actively studied for application to such a memory include lead zirconate titanate (Pb(ZrTi)O3; PZT), barium strontium titanate ((Ba,Sr)TiO3; BST), niobium strontium bismuth tantalate (SrBi2(Nb,Ta)2O9; SBT), and the like.
FIGS. 7A to 7C and FIGS. 8A to 8C are cross-sectional views showing the steps of a conventional method for manufacturing an electronic device, specifically, a conventional method for manufacturing a ferroelectric memory.
As shown in FIG. 7A, a gate electrode 13 is formed on an element formation region of a semiconductor substrate 10, the region surrounded by an element isolation region 11, with a gate insulating film 12 interposed therebetween. An insulating sidewall 14 is then formed on the side surface of the gate electrode 13. An impurity diffusion layer 15 is formed on both sides of the gate electrode 13 in the element formation region. The impurity diffusion layer 15 serves as a source region or a drain region. The gate electrode 13, the impurity diffusion layer 15 and the like form a MOS (metal oxide semiconductor) transistor 16 as a part of a peripheral element group.
As shown in FIG. 7B, a first interlayer insulating film 17 is formed on the semiconductor substrate 10 so as to cover the peripheral element group including the MOS transistor 16 by a CVD (chemical vapor deposition) method using a SiH4 gas-based material. The first interlayer insulating film 17 is formed from a BPSG (boro-phospho silicate glass) film. The first interlayer insulating film 17 is then planarized by a reflow process using heat treatment at 900° C.
As shown in FIG. 7C, an adhesion layer film 18, a lower electrode film 19, a ferroelectric thin film 20, an upper electrode film 21 and a silicon oxide film 22 are sequentially deposited on the first interlayer insulating film 17. The adhesion layer film 18 is formed from a conductive oxide such as TiOx (where x≧0). The lower electrode film 19 is formed from a conductive metal such as platinum. The ferroelectric thin film 20 is formed from SBT, PZT or the like. The upper electrode film 21 is formed from a conductive metal such as platinum. The silicon oxide film 22 serves as a mask material used to process the films 18 to 21. Thereafter, a resist pattern (not shown) is formed on the silicon oxide film 22. The resist pattern is used to pattern the lower electrode film 19 into predetermined dimensions to form a lower electrode. The films 18 to 22 are then patterned by etching, ion milling or the like. The films 18 to 22 thus patterned include a portion which will later serve as a ferroelectric thin film capacitor (see FIG. 8A) which forms a memory cell. Products by etching reaction (hereinafter, referred to as etching products), a residual resist material and the like produced by the step of FIG. 7C are then removed by, e.g., ashing and scrubber cleaning using ultra-pure water (hereinafter, referred to as ultra-pure water scrubber washing).
FIG. 9 schematically shows an example of the structure of an ultra-pure water scrubber cleaning device.
As shown in FIG. 9, a wafer 51, a substrate to be processed, is placed on a wafer stage 52 provided within a process cup (cleaning cup) 50. The wafer stage 52 is rotated by a motor 53. A nozzle 54 is provided above the wafer 51 within the process cup 50. Ultra-pure water is supplied from the outside of the process cup 50 to the nozzle 54 through an ultra-pure water supply pipe 55. The surface of the wafer 51 is cleaned with ultra-pure water 56 injected from the nozzle 54.
As shown in FIG. 8A, after the resist pattern (not shown) for patterning the upper electrode film 21 into predetermined dimensions to form an upper electrode is formed on the silicon oxide film 22, the silicon oxide film 22, the upper electrode film 21 and the ferroelectric thin film 20 are patterned by etching, ion milling or the like to form a ferroelectric thin film capacitor 23. Etching products, a residual resist material and the like produced by the step of FIG. 8A are then removed by ashing and ultra-pure water scrubber cleaning.
As shown in FIG. 8B, a second interlayer insulating film 24 is formed on the first interlayer insulating film 17 so as to cover the ferroelectric thin film capacitor 23 by a CVD method using an ozone TEOS (tetra ethyl ortho silicate) gas-based material. The second interlayer insulating film 24 is formed from a silicon oxide film. The second interlayer insulating film 24 is then planarized, and a plurality of contact holes 25 reaching the elements such as MOS transistor 16 and ferroelectric thin film capacitor 23 are formed in the first interlayer insulating film 17, the second interlayer insulating film 24 and the silicon oxide film 22. Etching products, a residual resist material and the like produced by the step of FIG. 8B are then removed by ashing and ultra-pure water scrubber cleaning.
As shown in FIG. 8C, extended wirings 26 for the elements such as MOS transistor 16 and ferroelectric thin film capacitor 23 are formed on the second interlayer insulating film 24 including the contact holes 25. A semiconductor integrated circuit having the elements electrically connected to each other is thus formed. Etching products, a residual resist material and the like produced by the step of FIG. 8C are then removed by ashing, cleaning using a polymer removing solution such as organic acid, and final washing using water.
Note that description and illustration of the steps following the step of FIG. 8C (such as the steps of forming an upper layer wiring, forming a protection film, and forming a pad portion) are omitted.
In the above conventional method for manufacturing an electronic device, ultra-pure water scrubber cleaning may be replaced with RCA cleaning or BHF (buffered hydrofluoric acid) cleaning.
It is widely known in the art that practical application of an electronic device having an element including an insulating metal oxide film (such as a ferroelectric memory) is hindered by degradation in characteristics of the element caused by water. The mechanism of such degradation is not known. However, it is dominantly considered that such degradation in characteristics of the element is caused by reduction of an oxide (i.e., a ferroelectric material or a high-k material). More specifically, heat treatment required in the step of forming a wiring and the like causes reaction between water contained in an insulating film and a wiring material such as aluminum and titanium, and hydrogen produced by the reaction reduces an oxide (a ferroelectric material or a high-k material).
In any case, any water molecules remaining in an insulating film or the like would cause reduction in dielectric strength of a ferroelectric thin film or a high dielectric constant thin film, or degradation in polarization characteristics (such as polarization reversal fatigue characteristics) of a ferroelectric material. This makes stable production of electronic devices difficult.
In the above conventional method for manufacturing an electronic device, however, water directly contacts the ferroelectric thin film 20 or the underlying first interlayer insulating film 17 in the cleaning step using a cleaning solution (specifically, ultra-pure water), i.e., the cleaning step conducted after the step of forming a lower electrode (the step of FIG. 7C) and the step of forming an upper electrode (the step of FIG. 8A).
Moreover, if the first interlayer insulating film 17 or the second interlayer insulating film 24 (each of which is formed from a BPSG film formed by a CVD method using a SiH4 gas-based material or a silicon oxide film formed by a CVD method using a ozone TEOS gas-based material) is planarized by a CMP (chemical mechanical polishing) method, water is used in the cleaning step following the planarizing step by a CMP method (post-planarization cleaning step). Therefore, water directly contacts each interlayer insulating film. Moreover, water contacts an exposed region of the surface of each interlayer insulating film in the cleaning step conducted after the step of forming contact holes and the step of forming a wiring.
It is known in the art that a BPSG film formed by a CVD method using a SiH4 gas-based material and a silicon oxide film formed by a CVD method using an ozone TEOS gas-based material, which are used as an interlayer insulating film, is generally likely to adsorb water. Water molecules adsorbed by or remaining in an interlayer insulating film or a ferroelectric film, the interface between various films, or the like can be removed by heat treatment such as high-temperature baking. However, it is impossible to control the thermal diffusion direction of the water molecules. Therefore, although some water molecules are removed to the outside of the device, other water molecules are diffused toward an element such as a ferroelectric capacitor, that is, toward the inside of the device, and thus remain within the device. It is impossible to prevent the latter water molecules from being diffused again by subsequent heat treatment of a metal wiring (such as sintering). Such diffusion of the water molecules would adversely affect ferroelectric characteristics and the like.
The same problems also occur in the case where an electronic device having an element using a high-k material such as BST (e.g., DRAM (Dynamic Random Access Memory)) is manufactured by the above conventional manufacturing method instead of a ferroelectric memory.